Advanced Design and Verification Trainee @ Maven Silicon · 0 yrs exp
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Experience
Advanced Design and Verification Trainee
Maven Silicon
Jul 2025 – Present · ~1.3 yrs
Gained hands-on training in SystemVerilog and UVM-based ASIC verification Developed testbenches for AXI and APB protocol verification environments Worked on assertions, functional coverage, and structured verification components
Education
Bachelor of Engineering Electronics and Communication Engineering
Canara Engineering College
2021 – 2012
Skills & stack
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